1. Field of the Invention
The present invention relates to a semiconductor device having structure that silicide layers of refractory metal or these of near-noble metal are selectively formed in surfaces of a diffusion layer and a gate electrode, a surface of capacitor electrode or the like, and to the method of producing the same.
2. Discussion of Background
FIG. 13 is a principal portion of semiconductor device in section made by a self aligned silicidation (SALICIDE) process according to a literature (Jun. 25-26, 1985 V-MIC Conf Proceeding). In the Figure, numeral 101 designates a semiconductor substrate; numeral 102 designates separation oxide films; numeral 103 designates a gate insulating film which is laminated on the-surface of the semiconductor substrate 101; numeral 104 designates a gate electrode laminated on the gate insulating film; numeral 105 designates a silicide layer formed by siliciding the surface of the gate electrode 104; numeral 106 designates source/drain regions made of a region including high concentration impurities and formed at both sides of the gate electrode 104 interposing a channel region positioned under the gate electrode 104; numeral 107 designates silicide layers formed by siliciding the surface of the source/drain regions 106; numeral 108 designates sidewalls formed by depositing on sides of the gate electrode 104 including sides of the silicide layer 105; numeral 109 designates insulating films laminated on an element including the gate electrode surface; numeral 110 designates bit wire contacts formed in the insulating layers 109 so as to contact surfaces of the source/drain regions 106.
In the semiconductor device as shown in FIG. 13, it was possible to obtain low resistance by siliciding the surface of gate electrode 104 and the surfaces of source/drain regions 106.
In the next, a flow of processing the semiconductor device of FIG. 13 is described with reference to FIGS. 14a through 14d. As shown in FIG. 14a, the separation oxide film 102 was formed on non-active areas in the surface of semiconductor substrate 101. Further, the gate electrode 104 was patterned in said surface after the gate insulating film 103 was formed. The source/drain regions 106 were formed by implanting impurities into the semiconductor substrate 101.
As shown in FIG. 14b, an oxide film such as TEOS was laminated on the whole surface of semiconductor substrate 101; and said whole surface was etched back, whereby the sidewalls 108 deposited on sides of the gate electrode 104 could selectively be leaved.
As shown in FIG. 14c, a refractory metal such as Ti or a near-noble metal 105a such as cobalt was laminated and the surfaces of source/drain regions 106 were silicided to obtain the silicide layers 105 and 107. At this time, in a surface layer, unreacted refractory metal or unreacted near-noble metal 105a was left.
Thereafter, as shown in FIG. 14d, the unreacted refractory metal or the unreacted near-noble metal 105 was taken off by liquid remover such as H.sub.2 SO.sub.4 and H.sub.2 O.sub.2. By providing the insulating film 109 and the bit wire contacts 110, it was possible to obtain the semiconductor device as shown in FIG. 13.
However, in general, when the silicide layers 107 were formed, the silicide layers 107 extended in a spike-like form to a PN junction between the source/drain regions 106 and the well, whereby it was known that there was a drawback that the leak current in the junction such as a field edge is large.
Therefore, although there was a merit that resistances of the diffusion layer and the gate electrodes could be small by the formation of silicide layers, it was not applicable to device sensitive to a junction leak, for example DRAM.
Another conventional technique disclosed in Japanese unexamined patent publication No. Hei. 5-259115 (JP-A-5259115) discloses a semiconductor device in which upper portions of gate electrodes and these of source/drain regions were selectively silicided for a first regions of device having transistor elements and no silicidation was provided in a second region of device having a high-resistance element including a region of impurities. There was also disclosed that a mask of SiO.sub.2 film is selectively formed on the second region of device so as not to silicide the second region of device.
On the other hand, a logic process consolidating DRAM was focused on in recent years, wherein a logic process for making a high-speed microprocessor and a DRAM are combined. This is a process for realizing both a high degree of integration of memory and a transistor having a high logic process in a chip.
In devices concerning multi-media which is recently paid attention to, a lage-sized memory and a high performance transistor for realizing a high-speed operation are necessary in order to perform operations of graphics. Also, the logic processing unit consolidating DRAM is necessary.
In the high-speed logic process, not only the high performance transistor but also resistances of a gate electrode and a diffusion layer such as a source/drain region had a great influence to delay, wherein the high-speed was obtainable by introducing the siliciding process.
However, in the logic process consolidating DRAM described as the convention technique, there were problems that failure in refreshing could be derived from by the junction leak concerning the siliciding process and, therefore, such a process was difficult to use.